1. Field of Invention
Various embodiments of the present invention relate generally to a method of operating a semiconductor device and, more particularly, to a program method.
2. Description of Related Art
A semiconductor device includes a memory cell array that stores data therein. The memory cell array consists of a plurality of cell blocks, each of which includes a plurality of cell strings. The cell strings have the same structure as each other, and are described below in more detail.
FIG. 1 is a circuit diagram illustrating a cell string.
With reference to FIG. 1, the cell string includes a drain select transistor, a plurality of memory cells, and a source select transistor that are all coupled in series with one another. A drain select line DSL is coupled to a gate of the drain select transistor, word lines WLn−k to WLn+k are coupled to respective gates of the memory cells, and a source select line SSL is coupled to a gate of the source select transistor. The drain select line DSL is commonly coupled to the other drain select transistors included in each cell string. Similarly, the word lines WLn−k to WLn+k and source select line SSL are each commonly coupled to other memory cells and source select transistors respectively, included in each cell string.
A method of programming a selected memory cell among the plurality of non-selected memory cells included in the aforementioned cell string is described below.
A program voltage Vpgm is applied to a selected word line WLn coupled to a selected memory cell 11, whereas a pass voltage Vpass is applied to unselected word lines WLn−1 to WLn−k and WLn+1 to WLn+k coupled to unselected memory cells. The selected memory cell 11 may be programmed by applying the program voltage Vpgm to the selected word line WLn once. One known method of a program operation, in order to reduce the distribution of threshold voltages of memory cells, has been performed by using the Incremental Step Pulse Program (ISPP) method, in which one of the steps allows for the program voltage Vpgm to gradually increase. Further details of the ISPP method is described below.
FIG. 2 is a graph illustrating a conventional program method.
With reference to FIGS. 1 and 2, a program operation using the ISPP method is performed in such a manner that the program voltage Vpgm is applied to the selected word line WLn and the pass voltage Vpass is applied to the unselected word lines WLn−1 to WLn−k and WLn+1 to WLn+k. In general, pass voltage Vpass is lower than program voltage Vpgm. Specifically, program voltage Vpgm is low at the initial stage of the program operation, and as the program operation is repeatedly performed, program voltage Vpgm is gradually increased. After the program voltage Vpgm and the pass voltage Vpass are applied to the word lines WLn−k to WLn+k, a verify operation is performed to determine whether a threshold voltage of the selected memory cell has reached a predetermined target level. Following the verify operation, the threshold voltage of the selected memory cell is assessed, in which if it has not reached the target level, both the program operation and the verify operation that apply the program voltage Vpgm and the pass voltage Vpass, respectively, are repeated while the program voltage Vpgm is step-increased until the threshold voltage of the selected memory cell reaches the target level. If the threshold voltage has reached the target level, the program operation is complete.
During the program operation, while the program voltage Vpgm gradually increases, the constant pass voltage Vpass(1) applied to the unselected word lines WLn−1 to WLn−k and WLn+1 to WLn+k maintains a constant level. Therefore, the voltage difference between the program voltage Vpgm and the constant pass voltage Vpass(1) gradually increases. During the program operation, an increasing pass voltage Vpass(2) may be applied to the remaining unselected word lines WLn−k to WLn−1 and WLn+1 to WLn+k. The increasing pass voltage Vpass(2) increases by a step-up level lower than that of the program voltage Vpgm.
Particularly, when the program voltage Vpgm applied to the selected word line WLn is above a predetermined level, unselected memory cells 12 adjacent to the selected memory cell 11 may be inadvertently erased. That is, while the program voltage Vpgm gradually increases, if the program voltage Vpgm rises above a critical voltage difference in reference to the pass voltage Vpass, a breakdown between the selected memory cell and the unselected memory cells may occur. Electrons which are stored in the floating gate of the unselected memory cells adjacent to the selected memory cell may be ejected to the control gate of the selected memory cell, thus decreasing the threshold voltages of the unselected memory cells. Additionally, as for unselected memory cells having completed the program operation among the unselected memory cells 12 adjacent to the selected memory cell 11, in the case that threshold voltages of these memory cells decrease, other data may be inadvertently read during a read operation subsequent to the program operation, which may reduce the reliability of the semiconductor device.
In other words, after the program voltage Vpgm being applied to the selected word line WLn gradually increases during the program operation in order for the voltage difference between the program voltage Vpgm and the pass voltage Vpass to reach the critical voltage difference CD, the threshold voltage of the selected memory cell and the threshold voltages of the neighboring memory cells may change, and leakage of the neighboring memory cells may be generated, which may lead to reduction in reliability of the program operation.